The rapid growth of artificial intelligence (AI), high-performance computing (HPC), and data-centric applications is driving a paradigm shift from conventional monolithic system-on-chip (SoC) architectures toward chiplet-based heterogeneous integration. Advanced packaging has consequently become a key enabling technology for achieving higher performance, greater functionality, improved power efficiency, and shorter development cycles. This short course introduces the fundamental concepts of advanced packaging for chiplet systems, covering major integration schemes, including 2.5D, 3D, fan-out, and wafer-level packaging technologies. Particular attention will be given to hybrid bonding, which is emerging as a critical technology for fine-pitch, high-density interconnects in next-generation semiconductor systems. The course will also highlight recent technological developments, industrial trends, and global research activities, while discussing remaining technical challenges and future directions toward AI-driven computing, CMOS 2.0, and heterogeneous system integration.