Jaber Derakhshandeh received the bachelor’s, master and Ph.D. degree all in electrical engineering. In 2013, he joined 3D system integration group at imec, where he is involved in exploratory projects in die-to-wafer and wafer-to-wafer (W2W) stacking for high-density interconnections and Quantum computing.

As solid-state quantum computing, encompassing both superconducting and semiconductor spin-qubit platforms, scales toward fault-tolerant regimes, traditional 2D planar architectures face severe spatial constraints. The increasing density of control and readout connections leads to routing congestion at the chip periphery, creating “wiring bottlenecks” that limit qubit connectivity and scalability. Transitioning to 3D heterogeneous packaging architectures on 300 mm silicon wafer platforms offers a promising path forward by enabling vertical signal delivery, fine-pitch routing, and modular integration for large-scale quantum systems. This talk will explore recent advances in quantum system packaging, with a focus on interposer architectures tailored to specific qubit modalities, through-silicon vias (TSVs), superconducting interconnect metallurgy, and high-precision bonding technologies developed on 300mm Si wafers.
The presentation is divided into two parts:
1. Superconducting Qubits
Dense control and readout interconnects can introduce dielectric losses that degrade qubit coherence and limit device performance. To mitigate these effects, an interposer wafer is employed to spatially separate the sensitive qubit layer from the lossy rerouting circuitry, creating a low-loss physical and electromagnetic buffer while preserving high-density signal delivery.
2. Spin Qubits
The extremely compact footprint of quantum-dot arrays demands highly scalable interconnection solutions. Wafer-to-wafer (W2W) bonding provides a high-density integration path through sub-micron-pitch interconnects. This approach enables the interposer to relax and fan out the dense qubit pitch to an active control-chiplet layer, offering a scalable route for the co-integration of spin-qubit quantum processing units (QPUs) with classical CMOS control electronics.

Darsen D. Lu received the B.S. degree in electrical engineering with special honors from National Tsing Hua University, Hsinchu, Taiwan, R.O.C., in 2005, and the M.S. and Ph.D. degrees in electrical engineering and computer sciences from the University of California Berkeley, in 2007 and 2011, respectively. His Ph.D. word focused on compact models for multiple gate cMOS, which led to the creation of industry standard compact models for FinFETs (BSIM-CMG) and UTB-SOI devices (BSIM-IMG). From 2011 to 2015, he was with IBM Research, Yorktown Heights, NY, USA, where he was involved with research and development for 14nm, 10nm and 7nm CMOS technologies and TCAD as well as 20nm phase change memory. He is currently a Macronix Endowed Chair Professor (Associate Professor) with the Department of Electrical Engineering at National Cheng Kung University, Tainan, Taiwan, R.O.C. He is a senior member of IEEE. His research interest includes design automation for quantum computation, modeling of cryogenic CMOS, and the fabrication, characterization, modeling, and design of ferroelectric memory.

As quantum computers scale up, a new computer-aided design framework is necessary to enable efficient large-scale design. In this invited talk, we first introduce quantum chiplet, a framework to combine gate-level design, quantum circuits in matrix form, and Verilog-synthesized digital quantum building blocks. In addition, the GQROM technique enables efficient state preparation utilizing the concept of Gray code. Furthermore, hardware efficient peak estimation readout method is illustrated by the estimation of Pi with quantum circuit.

Wagno Alves Bragança Júnior is an electrical engineer and PhD candidate at QuTech, TU Delft, specializing in advanced semiconductor packaging and heterogeneous integration for quantum computing. He brings extensive R&D experience in laser-assisted bonding (LAB) and advanced packaging technologies from his previous work at the Electronics and Telecommunications Research Institute, Daejeon, Republica of Korea, and JCET STATS ChipPAC, Incheon, Republic of Korea. His current research focuses on 3D integration and heterogeneous packaging solutions for quantum computers. He has authored seven peer-reviewed publications and holds five U.S. patents.

Modular quantum computer architectures require dense and reliable interconnections between quantum processor units and cryogenic control and readout electronics. This quantum–classical interface is essential for addressing the wiring bottleneck associated with scaling to large numbers of qubits. Indium is an attractive interconnection material because of its favorable electrical and mechanical properties at cryogenic temperatures; however, conventional indium bump fabrication and bonding techniques can be difficult to integrate into modular quantum architectures. In this work, we present two laser-assisted technologies for quantum–classical integration: laser soldering for the fabrication of indium micro bumps and laser-assisted bonding (LAB) for their flip-chip integration. The resulting test vehicle exhibited a critical temperature of approximately 8 K and a critical current of 18 mA. In addition, the assemblies withstood 100 thermal-shock cycles without electrical failure, while die-shear testing showed that ductile fracture within the indium solder remained the dominant failure mode. The presentation will discuss the fabrication processes, cryogenic electrical performance, and reliability of these interconnects, and their potential application to scalable quantum computing architectures.

Jargal Hepp is a Research Associate at Fraunhofer IIS in Erlangen, Germany, where he has been working since 2023 on RF and high-frequency interconnect solutions for cryogenic applications. His work focuses on the design and integration of highly integrated flexible waveguides and cryogenic RF interconnect technologies. He is also involved in PCB and packaging design, including the development of interface boards connecting flexible waveguides to interposer-based systems and ultimately to qubit chips using wire bonding and flip-chip bonding. He received his M.Sc. in Electrical Engineering from Friedrich-Alexander-Universität Erlangen-Nürnberg in 2023.

The development of scalable cryogenic RF systems requires reliable and highly integrated interconnect solutions spanning multiple packaging and integration technologies. This talk presents an approach to RF interconnect and packaging design, covering the signal path from flexible waveguides and PCB interfaces to interposer-based systems and qubit chips. A particular focus is placed on the challenges of maintaining RF performance and signal integrity across transitions between different technologies and physical interfaces. The design of a dedicated interface PCB connecting flexible waveguides to an interposer is discussed, together with the integration of the interposer with the qubit chip using wire bonding and flip-chip bonding. Key challenges related to electromagnetic design, impedance transitions, packaging constraints, mechanical integration, and cryogenic operation are addressed. The talk highlights practical design considerations and solutions for realizing robust, highly integrated RF interconnects in cryogenic quantum systems, with an emphasis on the co-design of PCB, interposer, packaging, and chip-level interconnects.